1 hv101 demo board supertex inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." supertex does not assume responsibility for use of devices described and limits its liabi lity to the replacement of devices determined to be defective due to workmanship. no responsibility is assumed for possible omissions or inaccuracies. circuitry and specifications are subject to c hange without notice. for the latest product specifications, refer to the supertex website: http://www.supertex.com. for complete liability information on all supertex products, refer to the most curre nt databook or to the legal/disclaimer page on the supertex website. HV101DB1 introduction the supertex HV101DB1 demo board contains all necessay circuitry to demonstrate the features of the hv100 hotswap controller. intended primarily as a negative hotswap controller, the hv101 controls the negative supply path. included on board is a 100 f capacitor (c 3 ) to provide a capacitive load for testing. additional capacitance may be connected to the v out terminals. or the 100 f may be removed altogether the board may be modified to meet custom requirements. instructions are provided on the next page for modifications. 3-pin hotswap controller specifications input voltage 10v to 72v peak inrush limit 1.4a typ max short circuit current 1 4a typ circuit breaker response time 1 1ms typ auto retry 2.5s typ on resistance 210mw_ max undervoltage trip 15v on, 14v off 1 during inrush limiting v in connect the supply voltage to these terminals. supply voltage may range from 10 volts to 72 volts. a high source impedance may cause oscillations when the input voltage is near the undervoltage trip point. a high source imped- ance results in a large voltage drop when loaded, causing undervoltage lockout to kick in, disconnecting the load. with the load removed, input voltage rises, causing undervoltage to release and reconnecting the load. the cycle repeats, resulting in oscillations. source impedance must be less than the follow- ing to avoid oscillations: r i source load = 15 .v v out connect the power supply or other load to these terminals. v out+ is connected to v in+ , it is v out that is switched. application of a dc load during start-up and/or additional load capacitance extends the time inrush limiting is active. if this time exceeds 100ms, the hv101 shuts off, retrying 2.5s later. for this reason, dc load at start-up should be less than 900ma. note that dc start-up load limitation decreases with added load capacitance. note that the circuit breaker functions during inrush only. board layout and connections q1 u1 c 3 r 1 c 2 r 2 c 1 drain v pp out vpp in v nn in alt q1 +out -out gate + current probe power supply or load v in v out 01/21/02
2 hv101 demo board 1235 bordeaux drive, sunnyvale, ca 94089 tel: (408) 744-0100 ?fax: (408) 222-4895 www.supertex.com 01/21/02 ?001 supertex inc. all rights reserved. unauthorized use or reproduction prohibited. a very high dv/dt on the input can overload the hv101 s internal gate clamp, causing turn-on transients. a capacitor in the c 2 position may be used to clamp the gate, preventing the tran- sients. a 1nf value is usually adequate. voltage rating should be 16 volts. to limit short-at-turn-on current, zero-ohm resistor r 1 may be replaced with a low value resistor. this resistor causes a voltage drop that tends to cancel-out the applied gate voltage, thus limiting drain current. to reduce peak inrush current, a capacitor from gate to drain (c 1 ) may be employed. a resistor (r 2 ) is also needed in this configu- ration for loop stability. please refer to the hv101 data sheet for further information. note: when making positive-ground measurements, scope probe loading on the gate pin may interfere with normal operation. to observe gate voltages, use negative-ground mea- surements. hv101 demo board schematic hv101 current probe gate v pp v nn c 1 not used c 2 not used r 2 not used c 3 100 f r 1 0 ? q 1 irfr120n v pp in v nn in out+ out- drain gate v pp ou t
|
